Compact High Speed Reconfigurable Hardware Implementation of RC4 Stream Cipher

RC4 Stream cipher is well known for its simplicity and ease to develop in software. But here, in the proposed design we have heighlighted the modified hardware implémentation of RC4. As RC4 is the most popular stream cipher. The proposed design performs reading and swapping simultaneously in one clock cycle. The proposed design also highlights the adder part which enhances the architecture speed. As this design uses fast Carry Look Ahead Adder as the adder logic. RC4 uses a variable length key from 1 to256 bytes to initialize a256-byte array. The array is used for subsequent generation of pseudo-random bytes and then generates a pseudorandom stream, which is XORed with the plaintext/cipher text to give the cipher text/plaintext. The RC4 stream cipher works in two phases. The key setup phase and the pseudorandom key stream generator phase. Both phases must be performed for every new key. The RC4 algorithm will be implemented by FPGA using VHDL software platform.